Barrier-less prefilled via formation

A method for fabricating a semiconductor device, comprising:

• forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench;
• after forming the one or more layers, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level;
• forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material in direct contact with the first conductive line;
• forming second conductive material on the barrier-less prefilled via and the one or more layers by performing a seed and plating process;
• and
• planarizing the second conductive material to form a second conductive line corresponding to a second metallization level in direct contact with the barrier-less prefilled via to reduce via resistance.

A method for fabricating a semiconductor device, comprising:

• forming one or more layers including at least a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench formed in the first ILD layer;
• after forming the one or more layers, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level;
• and
• forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material, the barrier-less prefilled via disposed in direct contact with the first conductive line.