Methods for producing a 3d semiconductor memory device

A method for producing a 3D memory device, the method comprising:

• providing a first level comprising a single crystal layer and control circuits,
• wherein said control circuits comprise a plurality of first transistors;
• forming at least one second level above said first level;
• performing a first etch step comprising etching holes within said second level;
• and
• performing additional processing steps to form a plurality of first memory cells within said second level,
• wherein a plurality of second transistors each comprise a channel, a source, and a drain having a same doping type,
• wherein each of said plurality of first memory cells comprises one of said plurality of second transistors,
• wherein said first memory cells are a NAND nonvolatile type memory,
• wherein said control circuits comprise memory peripheral circuits,
• wherein at least one of said plurality of first memory cells is at least partially atop a portion of said memory peripheral circuits, and
• wherein fabrication processing of said first transistors accounts for a temperature and time associated with said processing said second level and said second transistors by adjusting a process thermal budget of said first level accordingly.

A method for producing a 3D memory device, the method comprising:

• providing a first level comprising a single crystal layer and control circuits,
• wherein said control circuits comprise a plurality of first transistors;
• forming at least one second level above said first level;
• performing a first etch step comprising etching holes within said second level;
• performing additional processing steps to form a plurality of first memory cells within said second level,
• wherein each of said first memory cells comprise one of a plurality of second transistors,
• wherein said control circuits comprise memory peripheral circuits,
• wherein at least one of said first memory cells is at least partially atop a portion of said memory peripheral circuits, and
• wherein fabrication processing of said first transistors accounts for a temperature and time associated with said processing said second level and said plurality of second transistors by adjusting a process thermal budget of said first level accordingly.