Sensor for Performance Variation of Memory Read and Write Characteristics

A device comprising:

• a bitcell coupled to a wordline, a bitline and an ncored port;
• a first logic gate that provides a wordline signal to the bitcell via the wordline based on an enable signal and a supply voltage provided by the ncored port;
• a first transistor that provides the supply voltage to the bitline based on activation by the wordline signal;
• and
• a second transistor that discharges the bitline to ground based on activation by the wordline signal.

A device comprising:

• a first memory structure disposed in a first area, the first memory structure having first bitcells fabricated with first transistors;
• and
• a second memory structure disposed in a second area different than the first area, the second memory structure having second bitcells fabricated with second transistors,
• wherein the second transistors are configured to detect variation of at least one of read current and write current associated with the first transistors.