Analog nonvolatile memory cells using dopant activation
AssigneeInternational Business Machines Corporation
InventorsHeng Wu, Tenko Yamashita, Oleg Gluschenkov, Alexander Reznicek
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Abstract
Memory cells and methods of forming and operating the same include forming a doped crystalline semiconductor memory layer on a first electrode. The doped crystalline semiconductor memory layer has a programmable dopant activation level that determines a resistance of the doped crystalline semiconductor memory layer. A second electrode is formed on the doped crystalline semiconductor memory layer.
Claims20
A method of forming a memory cell, comprising:
- forming a doped crystalline semiconductor memory layer on a first electrode, the doped crystalline semiconductor memory layer having a programmable dopant activation level that determines a resistance of the doped crystalline semiconductor memory layer;
- and
- forming a second electrode on the doped crystalline semiconductor memory layer.
A method for storing a value in a doped crystalline semiconductor memory cell with a programmable dopant activation level, comprising:
- applying a first voltage pulse to a doped semiconductor memory cell, to set a resistance of the doped semiconductor memory cell to a low value, wherein the first voltage pulse has a magnitude that activates the dopant within a crystal structure of a base semiconductor material of the doped semiconductor memory cell by integrating the dopant into the crystal structure;
- applying a second voltage pulse to the doped semiconductor memory cell, to deactivate dopant within the crystal structure, by causing the dopant to precipitate out of the crystal structure, and to increase the resistance thereby.
A memory cell, comprising:
- a conductive first electrode;
- a doped crystalline semiconductor memory layer on the first electrode, having a programmable dopant activation level that determines a resistance of the doped crystalline semiconductor memory layer;
- and
- a conductive second electrode on the doped crystalline semiconductor memory layer.
Dependencies are inferred from the claim text.