A memory device comprising:
- a semiconductor substrate having a main surface extending in a first direction and a second direction crossing the first direction,
- a bit line provided on a side of the main surface in a third direction crossing the first direction and the second direction and extending the first direction;
- a first semiconductor pillar electrically connected to the bit line and extending in the third direction;
- a second semiconductor pillar electrically connected to the bit line and extending in the third direction;
- a first conductive member extending in the second direction and intersecting the first semiconductor pillar;
- a second conductive member extending in the second direction and intersecting the second semiconductor pillar, the first and second conductive members being at a same position in the third direction, the second conductive member being electrically disconnected from the first conductive member;
- a plurality of third conductive members arranged between the first conductive member and the semiconductor substrate in the third direction, each of the third conductive members extending in the second direction and intersecting the first semiconductor pillar;
- a plurality of fourth conductive members arranged between the second conductive member and the semiconductor substrate in the third direction, each of the fourth conductive members extending in the second direction and intersecting the second semiconductor pillar, the plurality of third conductive members and the plurality of fourth conductive members being at same positions in the third direction, respectively, and electrically connected to each other, respectively;
- a fifth conductive member provided between the plurality of third conductive members and the semiconductor substrate in the third direction, extending in the second direction, and intersecting the first semiconductor pillar;
- a sixth conductive member provided between the plurality of fourth conductive members and the semiconductor substrate in the third direction, extending in the second direction, and intersecting the second semiconductor pillar, the fifth and sixth conductive members being at a same position in the third direction;
- one or more seventh conductive members provided between the fifth conductive member and the semiconductor substrate in the third direction, each of the one or more seventh conductive members extending in the second direction and intersecting the first semiconductor pillar;
- and
- one or more eighth conductive members provided between the sixth conductive member and the semiconductor substrate in the third direction, each of the one or more eighth conductive members extending in the second direction and intersecting the second semiconductor pillar, the one or more seventh conductive members and the one or more eights conductive members being at same positions in the third direction, respectively, and electrically disconnected to each other, respectively.