Page buffer and memory device including the same

A programming method of at least one memory cell among a plurality of memory cells of a memory device, the programming method comprising:

• determining an operating mode of the memory device;
• determining whether a selected memory cell exists among the plurality of memory cells;
• supplying a bitline voltage higher than a ground voltage and lower than a power supply voltage to a bitline connected to the plurality of memory cells when a selected memory cell is one of the memory cells and the operating mode is a first mode;
• and
• supplying a predetermined bitline voltage to a bitline connected to the plurality of memory cells when a selected memory cell is one of the memory cells and the operating mode is a second mode.

A memory device comprising:

• a stacked structure disposed on a substrate, wherein the stacked structure comprises a plurality of gate electrode layers alternating with a plurality of insulating layers;
• one or more channel structures penetrating through the stacked structure, wherein the channel structures are disposed on an epitaxial layer connected to the substrate;
• and
• a wordline cut region penetrating through the stacked structure, wherein the wordline cut region is disposed between the channel structures, and dividing the gate electrode layers and insulating layers into a plurality of regions,
• wherein each of the channel structures comprises a channel layer and a gate insulating layer,
• the gate electrode layers comprise a ground select line, a string select line, and a plurality of wordlines disposed between the ground select line and the string select line,
• the wordlines and channel structures adjacent to the wordlines provide memory cells, and
• a thickness of the gate insulating layers increases and a bitline voltage input to a bitline connected to the memory cells decreases as a distance from the wordline cut region increases.