Voltage offset for compute-in-memory architecture
AssigneeQUALCOMM Incorporated
InventorsEdward Harrison Teague, Zhongze Wang, Max Welling
Life of this patent
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Abstract
In one embodiment, an electronic device includes a compute-in-memory (CIM) array that includes a plurality of columns. Each column includes a plurality of CIM cells connected to a corresponding read bitline, a plurality of offset cells configured to provide a programmable offset value for the column, and an analog-to-digital converter (ADC) having the corresponding bitline as a first input and configured to receive the programmable offset value. Each CIM cell is configured to store a corresponding weight.
Claims20
An electronic device comprising a compute-in-memory (CIM) array comprising a plurality of columns, wherein:
- each column comprises:
- a plurality of CIM cells connected to a read bitline;
- a plurality of offset cells configured to provide a programmable offset value for the column;
- and
- an analog-to-digital converter (ADC) having the read bitline as a first input and configured to receive the programmable offset value;
- and
- each CIM cell is configured to store a corresponding weight.
A method for an electronic device wherein:
- the electronic device comprises a compute-in-memory (CIM) array;
- the CIM array comprises a plurality of columns;
- each column comprises:
- a plurality of CIM cells connected to a read bitline;
- a plurality of offset cells;
- and
- an analog-to-digital converter (ADC) having the read bitline as a first input;
- the method comprising:
- storing a corresponding weight in each CIM cell;
- providing, to the ADC, by the plurality of offset values, a programmable offset value for the column.
Dependencies are inferred from the claim text.