Memory with symmetric read current profile

A memory, comprising:

• a first memory array configured to store first data;
• a second memory array configured to store second data;
• and
• a read circuit, comprising:
• a decoding circuit configured to provide a first signal according to the first data of the first memory array and a second signal according to the second data of the second memory array in response to a first address signal;
• a twist circuit configured to selectively provide one of the first signal and the second signal as a first exchange signal and selectively provide the other as a second exchange signal according to a first control signal;
• and
• an output buffer configured to selectively provide the first exchange signal or the second exchange signal as an output according to a second control signal,
• wherein binary representation of the first signal is complementary to that of the second signal.

A memory, comprising:

• a first memory array configured to store first data;
• a second memory array configured to store second data that is complementary to the first data;
• and
• a read circuit, comprising:
• a sense circuit configured to provide a first sensing signal according to a reference signal and the first data, and a second sensing signal according to the reference signal and the second data;
• a twist circuit configured to randomly provide one of the first sensing signal and the second sensing signal as a first signal and the other as a second signal;
• and
• an output buffer configured to selectively provide the first signal or the second signal as an output according to a control signal.