Partial refresh technique to save memory refresh power

An apparatus, comprising:

• a system-on-chip (SOC) configured to communicate with a memory device over a link,
• wherein the memory device comprises:
• a plurality of DRAM memory cells;
• a partial array refresh PAR enable register which comprises a partial array auto-refresh (PAAR) enable bit, wherein the PAAR enable bit indicates whether or not a PAAR is enabled;
• and
• a PAR mask register,
• wherein the SOC is configured to instruct the memory device to enter into a self-refresh mode to cause the memory device to refresh a subset of the memory cells selected in accordance with the PAR mask register without receiving refresh REF commands from the SOC when a partial array self-refresh (PASR) is enabled by a PASR enable bit set by the PAR enable register, and
• wherein the SOC is configured to issue the REF command to the memory device to cause the memory device to refresh the subset of the memory cells selected in accordance with the PAR mask register when the memory device is in an auto-refresh mode and the PAAR is enabled.

A method for reducing memory power consumption in an apparatus of a computing system,

• wherein the apparatus comprises a system-on-chip (SOC) and a memory device configured to communicate with each other over a link,
• wherein the memory device comprises:
• a plurality of memory cells;
• and
• a plurality of mode registers MR comprising a partial array refresh PAR enable register and a PAR mask register, the PAR enable register including a partial array self-refresh PASR enable bit and a partial array auto-refresh PAAR enable bit, the PASR enable bit indicating whether PASR is enabled or disabled, and the PAAR enable bit indicating whether PAAR is enabled or disabled, and
• wherein the method comprises:
• issuing, by the SOC, a mode register write MRW command with a corresponding mode value of the PAAR enable bit to the memory device;
• issuing, by the SOC, for each mode register used to implement the PAR mask register, a MRW command with a corresponding mode value to the memory device so as to cause a mask value to be written to the PAR mask register, the mask value corresponding to a refresh skip region;
• issuing, by the SOC, a REF command to the memory device;
• and
• skipping, by the memory device, refreshing of the refresh skip region based on the PAR mask register when the REF command is issued by the SOC and the PAAR enable bit is set.

An apparatus, comprising:

• a system-on-chip SOC configured to communicate with a memory device over a link,
• wherein the memory device comprises:
• a plurality of memory cells;
• a partial array refresh PAR enable register which comprises a partial array auto-refresh PAAR enable bit, wherein the PAAR enable bit indicates whether or not a PAAR is enabled;
• and
• a PAR mask register,
• wherein the SOC is configured to issue a refresh REF command to the memory device over the link to cause the memory device to refresh a subset of the memory cells selected in accordance with the PAR mask register when the memory device is in an auto-refresh mode and the PAAR is enabled on the memory device.