Semiconductor device, memory device, and electronic device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsTatsuya ONUKI, Takanori MATSUZAKI, Kiyoshi KATO, Shunpei YAMAZAKI
Life of this patent
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Abstract
A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.
Claims6
A memory device comprising:
- a bit line;
- a sense amplifier electrically connected to the bit line;
- a first memory cell array including a first write transistor and a first capacitor over the sense amplifier;
- a second memory cell array including a second write transistor and a second capacitor over the first memory cell array;
- and
- a third memory cell array including a third write transistor and a third capacitor over the second memory cell array,
- wherein the bit line extends in the second memory cell array in a horizontal direction, and
- wherein the bit line does not extend in the first memory cell array or in the third memory cell array in a horizontal direction.
A memory device comprising:
- a bit line;
- a sense amplifier including a selector and an equalizer electrically connected to the bit line;
- a first memory cell array including a first write transistor and a first capacitor over the sense amplifier;
- a second memory cell array including a second write transistor and a second capacitor over the first memory cell array;
- and
- a third memory cell array including a third write transistor and a third capacitor over the second memory cell array,
- wherein the bit line extends in the second memory cell array in a horizontal direction, and
- wherein the bit line does not extend in the first memory cell array or in the third memory cell array in a horizontal direction.
Dependencies are inferred from the claim text.