Semiconductor memory device having clock generation scheme based on command
AssigneeSamsung Electronics Co., Ltd.
InventorsSEUNGJUN SHIN, SU YEON DOO, TAEYOUNG OH
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Abstract
A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.
Claims20
A dynamic random access memory (DRAM) device comprising:
- a clock buffer configured to receive a system clock (CK) having a first frequency;
- a data clock buffer configured to receive a data clock (WCK) having a second frequency which is higher than the first frequency;
- a command decoder configured to receive a column address strobe (CAS) command for one of a write operation and a read operation and generate an auto-sync signal after a predetermined time from receiving the CAS command;
- and
- an internal data clock generating circuit configured to generate an internal data clock based on the data clock and synchronize phase of the internal data clock with phase of the system clock,
- wherein the data clock starts to toggle as the second frequency after the CAS command is received.
A method of clock synchronizing for a dynamic random access memory (DRAM) device, the method comprising:
- receiving a system clock (CK) having a first frequency;
- receiving a column address strobe (CAS) command for one of a write operation and a read operation;
- receiving a data clock (WCK) having a second frequency which is higher than the first frequency, the data clock starting to toggle as the second frequency after the CAS command is received;
- generating an internal data clock using the data clock;
- and
- internally synchronizing phase of the internal data clock with phase of the system clock after a predetermined time from receiving the CAS command.
A memory system comprising a memory controller and a memory device, wherein the memory device comprises:
- a clock buffer configured to receive a system clock (CK) having a first frequency;
- a data clock buffer configured to receive a data clock (WCK) having a second frequency which is higher than the first frequency;
- a command decoder configured to receive a column address strobe (CAS) command for one of a write operation and a read operation and generate an auto-sync signal after a predetermined time from receiving the CAS command;
- and
- an internal data clock generating circuit configured to generate an internal data clock based on the data clock and synchronize phase of the internal data clock with phase of the system clock,
- wherein the data clock starts to toggle as the second frequency after the CAS command is received, and
- wherein the memory controller is configured to send the CAS command for the one of the write operation and the read operation to the memory device and generate the data clock toggling after sending the CAS command.
Dependencies are inferred from the claim text.