US 2021/0343327 A1Published application

Memory controller device and phase calibration method

AssigneeRealtek Semiconductor Corp.

InventorJIE ZHENG

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Abstract

A memory controller device includes a delay line circuitry, data sampler circuits, phase detector circuits, and a control logic circuit. The delay line circuitry delays a data strobe signal to generate first to third clock signals, in which the second clock signal is for reading a data signal, and phases of the first to the third clock signals are sequentially differentiated by a predetermined value. The data sampler circuits sample the data signal according to the first to the third clock signals, in order to generate first to third signals. The phase detector circuits compare the first signal with the second signal to generate a first detection signal, and compare the third signal with the second signal to generate a second detection signal. The control logic circuit adjusts the first to the third clock signals according to the first and the second detection signals.

Claims20

Dependent claims

A memory controller device, comprising:

a delay line circuitry configured to delay a data strobe signal to generate a first clock signal, a second clock signal, and a third clock signal, wherein the second clock signal is for reading a data signal, and a phase of the first clock signal, a phase of the second clock signal, and a phase of third clock signal are sequentially differentiated by a predetermined value;
a plurality of data sampler circuits, wherein each of the plurality of data sampler circuits is configured to sample the data signal according to a corresponding one of the first clock signal, the second clock signal, and the third clock signal, in order to generate a corresponding one of a first signal, a second signal, and a third signal;
a plurality of phase detector circuits configured to compare the first signal with the second signal to generate a first detection signal, and to compare the third signal with the second signal to generate a second detection signal;
and
a control logic circuit configured to adjust the first clock signal, the second clock signal, and the third clock signal according to the first detection signal and the second detection signal.

2 more elements

A phase calibration method, comprising:

delaying a data strobe signal to generate a first clock signal, a second clock signal, and a third clock signal, wherein the second clock signal is for reading a data signal, and a phase of the first clock signal, a phase of the second clock signal, and a phase of third clock signal are sequentially differentiated by a predetermined value;
sampling the data signal according to a corresponding one of the first clock signal, the second clock signal, and the third clock signal, in order to generate a corresponding one of a first signal, a second signal, and a third signal;
comparing the first signal with the second signal to generate a first detection signal, and comparing the third signal with the second signal to generate a second detection signal;
and
adjusting the first clock signal, the second clock signal, and the third clock signal according to the first detection signal and the second detection signal.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/120,344Filed 14 Dec 2020
Priority: CN 202010355459.929 Apr 2020
Published: 4 Nov 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 11/4076
For memory cells of the field-effect type: timing circuits
G11C 7/1093
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: input synchronization
G11C 11/4093
Read-write [R-W] circuits: input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/1084
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input buffers,…

Family

US 11,302,380 B2Related patent
US 2021/0343327 A1This patent

From the US filing history. Foreign family members aren’t listed.

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