Power line communication driver circuit

A display device comprising:

• an array of LED zones each comprising one or more LEDs;
• a set of power communication lines;
• an array of distributed driver circuits to each control one or more of the LED zones, the array of distributed driving circuits arranged in groups, each group coupled to one of the set of power communication lines to receive a respective power line communication signal that supplies power to the driver circuits in the group and provides control data to the driver circuits in the group;
• a control circuit including a plurality of power line communication driver circuits for driving the set of power communication lines, each of the power line communication driver circuits comprising:
• a ramp generator circuit to receive an input signal encoding digital data and to generate a ramp signal that switches between a low non-zero ramp voltage and a high ramp voltage to encode the digital data;
• and
• a buffer circuit to receive the ramp signal and to buffer the ramp signal to generate the power line communication signal.

A control circuit for controlling groups of distributed zone integrated circuits each comprising one or more LEDs and a driver circuit for driving the one or more LEDs, the control circuit comprising:

• a timing controller to receive image data and to generate a plurality of timing signals each corresponding to one of the groups of distributed zone integrated circuits;
• a plurality of power line communication driver circuits, each of the plurality of power line communication driver circuits to receive one of the timing signals and to generate a power line communication signal to drive a power communication line coupled to one of the groups of distributed zone integrated circuits, the power line communication signal to supply power to the zone integrated circuits and to provide control data to the zone integrated circuits, each of the plurality of power line communication driver circuits comprising:
• a ramp generator circuit to receive the timing signal and to generate a ramp signal that switches between a low non-zero ramp voltage and a high ramp voltage to encode digital data of the timing signal;
• and
• a buffer circuit to receive the ramp signal and to buffer the ramp signal to generate the power line communication signal.