Ml-enabled assured microelectronics manufacturing: a technique to mitigate hardware trojan detection
AssigneeUniversity of Southern California
InventorsAjey Poovannummoottil JACOB, John DAMOULAKIS, Akhilesh JAISWAL, Devanand Krishna SHENOY, Andrew RITTENBACH
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Abstract
A method for assuring that integrated circuits are free of malicious circuit insertions and/or IC design modifications through mask swapping/addition is provided. The method includes a step of comparing 3D tomographic images constructed from design GDS to the 3D tomographic images constructed from in-line fab metrology data.
Claims26
A method for assuring that an integrated circuit is free of malicious circuit insertions and/or IC design modifications, the method comprising:
- constructing a first set of one or more tomographic images constructed from design GDS for an integrated circuit layer or layers;
- constructing a second set of one or more tomographic images from in-line fab metrology data for the integrated circuit layer or layers;
- and
- comparing corresponding images from first set of one or more tomographic images and the second set of one or more tomographic images to detect malicious circuit insertions and/or IC design modifications to the integrated circuit, corresponding imaging being images of the same integrated circuit region, wherein the presence of detect malicious circuit insertions and/or IC design are indicated by one or more differences between the corresponding images.
A method for assuring that an integrated circuit is free of malicious circuit insertions and/or IC design modifications, the method comprising:
- constructing a first set of one or more tomographic images constructed from design GDS for an integrated circuit layer or layers;
- constructing a second set of one or more tomographic images from SEM data for the integrated circuit layer or layers;
- and
- comparing corresponding images from first set of one or more tomographic images and the second set of one or more tomographic images to detect malicious circuit insertions and/or IC design modifications to the integrated circuit, corresponding imaging being images of the same integrated circuit region, wherein the presence of detect malicious circuit insertions and/or IC design are indicated by one or more differences between the corresponding images.
Dependencies are inferred from the claim text.