Ordering computations of a machine learning network in a machine learning accelerator for efficient memory usage
AssigneeSiMa Technologies, Inc.
InventorsReed Kotler, Nishit Shah
Life of this patent
Estimating the term…
Loading patent…
AssigneeSiMa Technologies, Inc.
InventorsReed Kotler, Nishit Shah
Estimating the term…
A compiler efficiently manages memory usage in the machine learning accelerator by intelligently ordering computations of a machine learning network. The compiler identifies a set of partial networks of the machine learning network representing portions of the machine learning network across multiple layers on which an output or set of outputs are dependent. Because any given output may depend on only a limited subset of intermediate outputs from the prior layers, each partial network may include only a small fraction of the intermediate outputs from each layer. Instead of implementing the MLN by computing one layer at a time, the compiler schedules instructions to sequentially implement partial networks. As each layer of a partial network is completed, the intermediate outputs can be released from memory. The described technique enables intermediate outputs to be directly streamed between processing elements of the machine learning accelerator without requiring large transfers to and from external memory.
A method for generating a computer program to implement a machine learning network on a machine learning accelerator (MLA), the MLA comprising one or more meshes of interconnected processing elements implemented on a semiconductor die, the method comprising:
A method for generating a computer program to implement a machine learning network on a machine learning accelerator (MLA), the MLA comprising one or more meshes of interconnected processing elements implemented on a semiconductor die, the method comprising:
A system comprising a machine learning accelerator (MLA) implemented on a semiconductor die, the MLA comprising:
Dependencies are inferred from the claim text.