Prefetch store preallocation in an effective address-based cache directory

A method of data processing in a processing unit, the method comprising:

• prefetching data likely to be accessed by a processor core of the processing unit into a vertical cache hierarchy including at least a store-through upper-level cache and a store-in lower-level cache, wherein the upper-level cache includes a data array and an effective address (EA) directory having a plurality of directory entries each corresponding to a respective data entry among a plurality of data entries in the data array;
• processing, in an execution of the processor core, memory access instructions and, based on processing the memory access instructions, initiating accesses to the vertical cache hierarchy;
• initiating a store prefetch stream, and based on store prefetch stream, allocating a directory entry in the EA directory for a store target EA in a store prefetch stream without prefetching a cache line of data into the corresponding data entry in the data array;
• and
• translating the store target EA into real address (RA) and caching in the directory entry EA-to-RA address translation information for the store target EA, such that a subsequent demand store access that hits in the directory entry can avoid a performance penalty associated with address translation.

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a processing unit, including:
• a vertical cache hierarchy including at least a store-through upper-level cache and a store-in lower-level cache, wherein the upper-level cache includes a data array and an effective address (EA) directory having a plurality of directory entries each corresponding to a respective data entry among a plurality of data entries in the data array;
• a processor core including:
• an execution unit configured to process memory access instructions and, based on processing the memory access instructions, initiate accesses to the vertical cache hierarchy;
• a translation unit configured to translate EAs to real addresses (RAs);
• a prefetch unit that prefetches data into the vertical cache hierarchy for access by the processor core, wherein the prefetch unit is configured to initiate allocation of a directory entry in the EA directory for a store target EA without prefetching a cache line of data into the corresponding data entry in the data array;
• and
• wherein the processor core caches in the directory entry EA-to-RA address translation information for the store target EA, such that a subsequent demand store access that hits in the directory entry can avoid a performance penalty associated with address translation by the translation unit.