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US 2021/0342231 A1Published application
High performance persistent memory
AssigneeRambus Inc.
InventorsFrederick A. Ware, Joseph James Tringali, Ely Tsern
Life of this patent
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Abstract
The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.
Claims21
(canceled)
A buffer device of a memory system, the buffer device comprising:
- a first interface to couple to one or more memory devices of a first memory type;
- a second interface to couple to one or more memory device of a second memory type, wherein the first memory type is volatile memory and the second memory type is non-volatile memory;
- and
- a control element coupled to the first interface and the second interface, wherein the control element is to:
- capture an initial base image of data in the one or more memory devices of the first memory type;
- store the initial base image in the one or more memory devices of the second memory type;
- track incremental updates to the data in the one or more memory devices of the first memory type;
- and
- transfer the incremental updates to the one or more memory devices of the second memory type;
- determine whether a system failure has occurred;
- and
- when the system failure has occurred, restore the initial base image and any of the incremental updates into the one or more memory devices of the first memory type.
9 more elements
An integrated circuit comprising:
- a first interface to couple to one or more memory devices of a first memory type;
- a second interface to couple to one or more memory device of a second memory type, wherein the first memory type is volatile memory and the second memory type is non-volatile memory;
- and
- a digital circuit coupled to the first interface and the second interface, wherein the digital circuit is to:
- capture an initial base image of data in the one or more memory devices of the first memory type;
- store the initial base image in the one or more memory devices of the second memory type;
- track incremental updates to the data in the one or more memory devices of the first memory type;
- and
- transfer the incremental updates to the one or more memory devices of the second memory type;
- determine whether a system failure has occurred;
- and
- when the system failure has occurred, restore the initial base image and any of the incremental updates into the one or more memory devices of the first memory type.
9 more elements
A memory system comprising:
- a buffer device access one or more memory devices of a first memory type;
- and
- an integrated circuit coupled to the buffer device and one or more memory devices of a second memory type, wherein the first memory type is volatile memory and the second memory type is non-volatile memory, and wherein the integrated circuit is to:
- receive, from the buffer device, an initial base image of data in the one or more memory devices of the first memory type;
- store the initial base image in the one or more memory devices of the second memory type;
- track incremental updates to the data in the one or more memory devices of the first memory type;
- and
- transfer the incremental updates to the one or more memory devices of the second memory type;
- determine whether a system failure has occurred;
- and
- when the system failure has occurred, restore the initial base image and any of the incremental updates into the one or more memory devices of the first memory type.
8 more elements
Dependencies are inferred from the claim text.