Method for implementing a line speed interconnect structure

A processor device, comprising:

• a scheduler to select from a plurality of computer instructions for dispatch;
• a pipeline to process the computer instructions;
• and
• a remapper coupled to the scheduler and pipeline, the remapper configured to
• receive the plurality of computer instructions, perform a pre-sorting of the plurality of computer instructions by a first stage to order the plurality of computer instructions, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of computer instructions in parallel to map the plurality of computer instructions from a first position to a second position based on a number of microoperations in each of the plurality of computer instructions, perform combining and splitting of the plurality of computer instructions by a second stage, and forwarding the plurality of computer instructions to a next processing stage in the pipeline at pipeline speed.

A computer system, comprising:

• a main memory;
• and
• a processor coupled to the main memory, the processor including a remapper, the remapper configured to
• receive a plurality of computer instructions, perform a pre-sorting of the plurality of computer instructions by a first stage to order the plurality of computer instructions, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of computer instructions in parallel to map the plurality of computer instructions from a first position to a second position based on a number of microoperations in each of the plurality of computer instructions, perform combining and splitting of the plurality of computer instructions by a second stage, and forwarding the plurality of computer instructions to a next processing stage in a pipeline at pipeline speed.