System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network

A system comprising:

• an interconnection network having a first plurality of communication lines for transmitting a packet header and a second plurality of communication lines for transmitting a data payload;
• a plurality of configurable circuits arranged in an array;
• and
• a processor coupled to the interconnection network, the processor comprising:
• a processor core configured to execute a plurality of instructions;
• and
• a core control circuit coupled to the processor core, the core control circuit comprising:
• an interconnection network interface coupled to the interconnection network, the interconnection network interface configured to receive a work descriptor data packet and to decode the received work descriptor data packet into an initial program count for an execution thread and a received argument for the execution thread;
• a network command queue coupled to the processor core;
• a thread control memory coupled to the interconnection network interface, the thread control memory comprising a thread identifier register configured to store a first plurality of thread identifiers, a thread state register, a program count register configured to store the initial program count, a data cache, and a general-purpose register configured to store the received argument;
• an execution queue coupled to the thread control memory, the execution queue configured to store one or more thread identifiers of the first plurality of thread identifiers;
• a control logic and thread selection circuit coupled to the execution queue and to the thread control memory, the control logic and thread selection circuit configured, in response to a work descriptor data packet having the initial program count and the received argument, to assign a thread identifier of the first plurality of thread identifiers to an execution thread and to place the thread identifier in the execution queue, the control logic and thread selection circuit further configured to select the thread identifier for execution of the execution thread by the processor core;
• and
• an instruction cache coupled to the processor core and to the control logic and thread selection circuit, the instruction cache configured to receive the initial program count and to provide to the processor core a corresponding instruction, of the plurality of instructions, for the execution thread;
• wherein the processor core is further configured to execute a fiber create instruction to generate and provide one or more commands to the network command queue, and wherein in response to the one or more commands in the network command queue, the interconnection network interface is further configured to generate and transmit one or more call work descriptor packets to the array of the plurality of configurable circuits for execution of a corresponding plurality of execution threads.

A system comprising:

• an interconnection network;
• a processor coupled to the interconnection network, the processor comprising:
• a processor core configured to execute a plurality of instructions;
• and
• a core control circuit coupled to the processor core, the core control circuit comprising:
• an interconnection network interface coupled to the interconnection network, the interconnection network interface configured to receive a work descriptor data packet and to decode the received work descriptor data packet into an initial program count for an execution thread and a received argument for the execution thread a thread control memory coupled to the interconnection network interface, the thread control memory comprising a thread identifier register configured to store a plurality of thread identifiers, a program count register configured to store the initial program count, and a data cache or a general-purpose register configured to store the received argument;
• an execution queue coupled to the thread control memory;
• and
• a control logic and thread selection circuit coupled to the execution queue and to the thread control memory, the control logic and thread selection circuit configured, in response to the received work descriptor data packet, to assign a thread identifier of the plurality of thread identifiers to the execution thread and to place the thread identifier in the execution queue, the control logic and thread selection circuit further configured to select the thread identifier for execution of a corresponding instruction, of the plurality of instructions, by the processor core;
• and
• a plurality of configurable circuits arranged in an array, each configurable circuit, of the array of the plurality of configurable circuits, comprising:
• a configurable computation circuit;
• a plurality of synchronous network inputs coupled to the configurable computation circuit;
• a plurality of synchronous network outputs coupled to the configurable computation circuit;
• and
• a configuration memory circuit coupled to the configurable computation circuit, to the plurality of synchronous network inputs, and to the plurality of synchronous network outputs, the configuration memory circuit comprising:
• a first instruction memory configured to store a first plurality of data path configuration instructions to configure a data path of the configurable computation circuit;
• and
• a second instruction memory configured to store a second plurality of data path configuration instructions or instruction indices for selection of a current data path configuration instruction from the first plurality of data path configuration instructions for the configurable computation circuit and for selection of a master synchronous network input of the plurality of synchronous network inputs for receipt of the current data path configuration instruction or instruction index from an adjacent configurable circuit of the array of the plurality of configurable circuits.