Handling load-exclusive instructions in apparatus having support for transactional memory

A data processing method comprising:

• in response to a load-exclusive instruction specifying a given address, setting an exclusive monitor indication for the given address;
• in response to a store-exclusive instruction specifying the given address, returning a store-exclusive fail indication when the given address no longer has the exclusive monitor indication set;
• in response to a predetermined type of load instruction specifying a load target address, which is executed within a transaction, clearing any exclusive monitor indication previously set for the load target address, the transaction comprising instructions of a given thread executed speculatively between a transaction start instruction and a transaction end instruction, for which commitment of results of the speculatively executed instructions is prevented until the transaction end instruction is reached, where the transaction is to be aborted in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction;
• and
• in response to said load-exclusive instruction, triggering an abort of a transaction for which the given address is specified as one of the working set of addresses.

A computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of threads of data processing;

• the computer program comprising:
• processing program logic to process threads of data processing;
• and
• transactional memory program logic to support execution of a transaction within a thread processed by the processing program logic, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing program logic is configured to prevent commitment of results of the speculatively executed instructions until the transaction end instruction is reached, the transaction memory program logic comprising conflict detection program logic to trigger an abort of the transaction in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction;
• in which:
• in response to a load-exclusive instruction specifying a given address, the processing program logic is configured to set an exclusive monitor indication for the given address;
• in response to a store-exclusive instruction specifying the given address, the processing program logic is configured to return a store-exclusive fail indication when the given address no longer has the exclusive monitor indication set;
• in response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, the processing program logic is configured to trigger clearing of any exclusive monitor indication previously set for the load target address;
• and
• in response to said load-exclusive instruction, at least one of the processing program logic and the transactional memory program logic is configured to trigger an abort of a transaction for which the given address is specified as one of the working set of addresses.

An interconnect comprising:

• a plurality of interfaces to exchange messages with a plurality of processing elements;
• and
• control circuitry configured to manage coherency between the plurality of processing elements;
• in which:
• in response to an exclusive monitor setting message from a given processing element indicating setting of an exclusive monitor indication associated with a given address for tracking exclusive access to the given address, the control circuitry is configured to trigger the interfaces to transmit the exclusive monitor setting message to at least one other processing element;
• and
• in response to a predetermined type of read request received from a first processing element requesting return of a read data value associated with a target address specified by the first type of read request, the control circuitry is configured to trigger the interfaces to transmit an exclusive monitor cancelling message to at least one other processing element to trigger cancellation of any exclusive monitor indication associated with the target address.