US 2021/0342134 A1 · CODE PREFETCH INSTRUCTION

Abstract

Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

Claims20

Dependent claims

An apparatus comprising:

an instruction decoder to decode a code prefetch instruction, wherein the code prefetch instruction is to specify a first instruction to be prefetched;
load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction;
and
execution circuitry to execute the first instruction at a fetch stage of a pipeline.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

17/033,751Filed 26 Sep 2020

Priority

29 Apr 2020

Published

4 Nov 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 8/4442
Reducing the execution time required by the program code: reducing the number of cache misses; Data prefetching
G06F 9/30047
To perform operations on memory: prefetch instructions; cache control instructions
G06F 9/3802
Concurrent instruction execution, e.g. pipeline or look ahead: instruction prefetching
G06F 12/0862
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with prefetch

Code prefetch instruction

Life of this patent

Code prefetch instruction

Life of this patent

Abstract

Claims20