Processing with compact arithmetic processing element

A device comprising:

• at least one instruction memory adapted to store at least one instruction;
• a plurality of low precision high dynamic range (LPHDR) execution units, wherein each LPHDR execution unit is adapted to execute a first operation on a first input signal that is a floating-point representation of a first numerical value to produce a first output signal representing a second numerical value, wherein the first operation is multiplication and wherein at least one LPHDR execution unit has access to memory local to that LPHDR execution unit;
• and
• circuitry adapted to decode at least one instruction received from the at least one instruction memory and to send at least one control signal to at least one LPHDR execution unit to cause the at least one LPHDR execution unit to operate according to the at least one instruction;
• wherein the floating-point representation has a binary mantissa at most as wide as 11 bits and a binary exponent at least as wide as 6 bits;
• wherein a number of LPHDR execution units in the device exceeds, by at least 20 more than three times, a non-negative integer number of high-precision execution units in the device adapted to execute the operation of multiplication on floating point numbers that are at least 32 bits wide;
• wherein at least one of the LPHDR execution units is smaller than at least one of the high-precision execution units;
• and
• wherein the plurality of LPHDR execution units are adapted to collectively perform, per cycle, at least tens of thousands of the first operations.