Data processing system including plurality of memory systems

A data processing apparatus comprising:

• a main memory system including first to third interfaces and a main storage region, coupled to a host through the first interface, and configured to set a size of logical-to-physical (L2P) mapping of the main storage region to a reference size unit;
• a first sub memory system including a fourth interface coupled to the second interface to communicate with the main memory system, and configured to transmit first capacity information for a first storage region included therein to the main memory system according to a request of the main memory system during an initial operation period, and set a size of logical-to-physical (L2P) mapping of the first storage region to a first size unit in response to a first map setting command transmitted from the main memory system during the initial operation period;
• and
• a second sub memory system including a fifth interface coupled to the third interface to communicate with the main memory system, and configured to transmit second capacity information for a second storage region included therein to the main memory system according to a request of the main memory system during the initial operation period, and set a size of logical-to-physical (L2P) mapping of the second storage region to a second size unit in response to a second map setting command transmitted from the main memory system during the initial operation period.