Neuromorphic computing device and operating method thereof

An operating method of a neuromorphic computing device comprising a first memory cell array comprising main resistive memory cells and a second memory cell array comprising reference resistive memory cells, the method comprising:

• activating all reference word lines connected to the second memory cell array;
• obtaining at least one reference voltage value based on at least one reference current output from the second memory cell array;
• and
• outputting a plurality of digital signals by converting signal voltage values corresponding to read currents output from the first memory cell array using the at least one reference voltage value.

A neuromorphic computing device comprising:

• a first resistive memory cell array comprising a plurality of resistive memory cells disposed in a region where a plurality of word lines intersect with a plurality of bit lines;
• a second resistive memory cell array comprising a plurality of reference resistive memory cells disposed in a region where a plurality of reference word lines intersect with a plurality of reference bit lines;
• a word line driver configured to drive the plurality of word lines and the plurality of reference word lines, activate at least one selected word line among the plurality of word lines according to element values of an input feature vector, and activate all of the plurality of reference word lines;
• a current-to-voltage converting circuit configured to convert a plurality of reference currents output from the second resistive memory cell array to a plurality of reference voltages through electrical paths comprising the plurality of reference bit lines, and convert a plurality of read currents output from the first resistive memory cell array to a plurality of signal voltages through electrical paths comprising the plurality of bit lines according to the activating of the at least one selected word line;
• an analog-to-digital converting circuit configured to convert the plurality of signal voltages to a plurality of digital signals and output the plurality of digital signals, using the plurality of reference voltages as a reference for analog-to-digital conversion;
• and
• an adder circuit configured to generate at least one piece of output data by performing an accumulation and/or summation operation using the plurality of digital signals.