Hardware Accelerated Discretized Neural Network

A device comprising:

• at least one digital-to-analog converter (DAC) configured to convert a digital input signal into an analog input signal;
• a plurality of non-volatile memory (NVM) weight arrays configured to compute a plurality of vector matrix multiplication (VMM) arrays based on the analog input signal, wherein:
• the plurality of NVM weight arrays is coupled to the at least one DAC;
• and
• multiple parallel NVM cells in the plurality of NVM weight arrays represent one synaptic weight element;
• at least one analog-to-digital converter (ADC) coupled to the plurality of NVM weight arrays, wherein the at least one ADC is configured to convert the VMM arrays into digital VMM values;
• and
• a neural circuit configured to process the digital VMM values through at least one activation function unit.

A circuit, comprising:

• means for converting a digital input signal into an analog input signal;
• means for converting a digital previous hidden state (PHS) signal into an analog PHS signal;
• means for computing a plurality of vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal;
• means for converting the VMM arrays into digital VMM values;
• and
• means for processing the digital VMM values into a new hidden state.