Twiddle factor generating circuit for an ntt processor

A circuit generating twiddle factors (400) on at least one finite field (Zp), for an NTT stream processor, said generating circuit being designed to generate at least one sequence of N twiddle factors {ψ0, ψ1, ψ2, . . . , ψN−1} wherein ψ is a root of unity in this field, wherein:

• at least one cache management module comprising a cache memory and a local controller controlling write and read in the cache memory;
• a modular multipliers bank comprising a plurality of W modular multipliers operating in parallel, each modular multiplier performing one multiplication on said field of two operands derived from a word read from the cache memory;
• a central controller initialising the cache memory with the G first twiddle factors of the sequence and controlling the cache manager so as, in each calculation cycle of a plurality T=N/W of calculation cycles, to supply a word read from the cache memory to the modular multipliers bank, to write a word into the cache memory at the end of each calculation cycle except for the last of said plurality, comprising the W results output from said modular multipliers, and to provide these W results at the end of each calculation cycle at the output from the generator, as W consecutive twiddle factors of said series.