System and method to accelerate reduce operations in graphics processor
AssigneeIntel Corporation
InventorsYong JIANG, Yuanyuan Li, Jianghong Du, Kuilin Chen, Thomas A. Tetzlaff
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AssigneeIntel Corporation
InventorsYong JIANG, Yuanyuan Li, Jianghong Du, Kuilin Chen, Thomas A. Tetzlaff
Estimating the term…
Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.
-25. (canceled)
An apparatus comprising:
A method comprising:
At least one computer-readable medium having stored thereon instructions which, when executed, causes a computing device to perform operations comprising:
Dependencies are inferred from the claim text.