Method and apparatus for renaming source operands of instructions

A processor comprising:

• a fetch and decode unit configured to output a group of one or more instructions;
• a free list configured to output a first physical register identifier of a first physical register allocated to a first instruction with a first destination operand from the group;
• one or more circuits, wherein a first circuit from the one or more circuits comprises a first decoder and a first plurality of 2-to-1 multiplexers, wherein a first 2-to-1 multiplexer from the first plurality of 2-to-1 multiplexers is coupled to receive the first physical register identifier, wherein the first decoder is coupled to receive the first destination operand, wherein a first output signal line from the first decoder is coupled as selection control to the first 2-to-1 multiplexer, wherein the first output signal line is asserted if the first destination operand is equal to a first architectural register, wherein the first 2-to-1 multiplexer outputs the first physical register identifier if the first signal line is asserted.

A method for renaming source operands of instructions comprising:

• receiving a group of instructions I(1), I(2), . . . , I(n);
• allocating physical registers to instructions with destination operand;
• maintaining a renaming register with a plurality of fields, wherein a first physical register identifier from architectural to physical register mappings is stored in a first field, wherein the first physical register identifier identifies a first physical register allocated to youngest instruction from prior group of instructions with destination operand equal to a first architectural register.