Generating a vector predicate summary

A method comprising:

• performing vector data processing in a subset of multiple parallel processing lanes determined by bit values of a vector predicate which are set;
• and
• generating a predicate summary value in dependence on the bit values of the vector predicate,
• wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition being true when the bit values of the vector predicate comprise a set bit corresponding to a vector element at a higher index immediately followed by a non-set bit corresponding to a vector element at a lower index,
• and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate.

A computer program for controlling a host data processing apparatus to provide an instruction execution environment comprising:

• vector processing logic to perform data processing in multiple parallel processing lanes, wherein the data processing is performed in a subset of the multiple parallel processing lanes determined by bit values of a vector predicate which are set;
• and
• predicate monitoring logic responsive to the vector predicate to generate a predicate summary value in dependence on the bit values of the vector predicate,
• wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition being true when the bit values of the vector predicate comprise a set bit corresponding to a vector element at a higher index immediately followed by a non-set bit corresponding to a vector element at a lower index,
• and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate.