Method for accessing flash memory module and associated flash memory controller and electronic device

A flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of block, each block is implemented by a plurality of word lines, each word line corresponds to a plurality of pages, each word line comprises a plurality of memory cells supporting a plurality of states, each memory cell is arranged to store a plurality of bits, each state represents different combination of the plurality of bits, and the flash memory controller comprising:

• a memory, for storing a program code;
• a microprocessor, for executing the program code to access the flash memory module via a control logic circuit;
• and
• a decoder;
• wherein the microprocessor reads the memory cells of at least a first word line of a specific block of the plurality of blocks to obtain a cumulative distribution information of the states of the memory cells, and the microprocessor determines a target decoding flow selected from at least a first decoding flow and a second decoding flow according to the cumulative distribution information, wherein the first decoding flow and the second decoding flow have different decoding methods or different decoding orders;
• and the microprocessor further reads the memory cells of a second word line to obtain readout information of the second word line, and the decoder uses the target decoding flow to decode the readout information of the second word line.

An electronic device, comprising:

• a flash memory controller;
• a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of block, each block is implemented by a plurality of word lines, each word line corresponds to a plurality of pages, each word line comprises a plurality of memory cells supporting a plurality of states, each memory cell is arranged to store a plurality of bits, each state represents different combination of the plurality of bits;
• wherein the flash memory controller reads the memory cells of at least a first word line of a specific block of the plurality of blocks to obtain a cumulative distribution information of the states of the memory cells, and the flash memory controller determines a target decoding flow selected from at least a first decoding flow and a second decoding flow according to the cumulative distribution information, wherein the first decoding flow and the second decoding flow have different decoding methods or different decoding orders;
• and the flash memory controller further reads the memory cells of a second word line to obtain readout information of the second word line, and the flash memory controller uses the target decoding flow to decode the readout information of the second word line.