System for Accelerated Training of Bit Output Timings

A storage device, comprising:

• a controller memory and a die memory;
• a controller configured to store first data in the controller memory, to transfer second data to the die memory over a bus having an n-bit width, to receive n bits of the second data from the die memory based on a data strobe, and to compare n bits of the first data with the n bits of the second data to produce n bit results, wherein the data strobe is offset with respect to a first one of the n bits of the second data by a first timing, and wherein the data strobe is offset with respect to a second one of the n bits of the second data by a second timing;
• and
• a plurality of accumulators each corresponding to one of the n bit results and including a first accumulator and a second accumulator, wherein the controller is further configured to update the first accumulator in response to a first one of the n bit results indicating a first mismatch, and to simultaneously update the second accumulator in response to a second one of the n bit results indicating a second mismatch;
• wherein the controller is further configured to determine whether a first value of the first accumulator or a second value of the second accumulator meet a mismatch threshold, to modify the first timing when the first value meets the mismatch threshold, and to modify the second timing when the second value meets the mismatch threshold.

A storage device, comprising:

• a controller memory and a die memory;
• a controller configured to store first data in the controller memory, to transfer second data to the die memory over a bus having an n-bit width, and to compare n bits of the first data with n bits of the second data to produce n bit results;
• and
• a plurality of accumulators each corresponding to one of the n bit results and including a first accumulator and a second accumulator, wherein the controller is further configured to update the first accumulator in response to a first one of the n bit results indicating a first mismatch, and to simultaneously update the second accumulator in response to a second one of the n bit results indicating a second mismatch;
• wherein the controller is further configured to determine whether at least one of a first value of the first accumulator or a second value of the second accumulator does not meet an entropy threshold, and to identify an error associated with the second data based on the determination.