Memory device having a secure test mode entry

A memory device, comprising:

• an array of memory cells;
• and
• an access management architecture providing a secure access to a test mode of the array of memory cells, the access management architecture comprising:
• a register group comprising data identifying the memory device;
• a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness;
• a non-volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature;
• and
• a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to the test mode of the array of memory cells.

A method for managing access to a memory array, comprising:

• providing data identifying a memory device including the memory array, along with specific data to a cryptographic algorithm;
• calculating an internal signature;
• verifying data freshness;
• prompting a user to insert a previously provided signature;
• comparing the internally calculated signature with the user provided signature;
• and
• allowing access to the memory array in a test mode in case of matching signatures.

A system, comprising:

• a System-on-Chip (SoC) component including a memory device, the memory device comprising:
• an array of memory cells;
• and
• an access management architecture providing a secure access to a test mode of the array of memory cells, the access management architecture comprising:
• a register group comprising data identifying the memory device;
• a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness;
• a non-volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature;
• and
• a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to a test mode of the array of memory cells.