US 2021/0333326 A1 · Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Without Known Good Die

Abstract

A Switching Mode Interposer (SMI) arrangement for boundary-scan testing of a Multi-Chip Module having a System-On-Chip, a Microprocessor Control Unit, and multiple chiplets-based devices including central processing units, graphical processing units, and/or memory devices disposed on a two-tiered interposer-substrate system. The SMI includes (a) a twin Test Access Port connected to a JTAG controller and configured to transmit test data in one direction (TAP-X) and an opposite direction (TAP-Y) along an Inter-Integrated Circuit (I2C) bus connected with the SOC, the MCU and the multiple devices, the test data being formatted according to IEEE 1149.1 or IEEE 1149.7 standard; and (b) a Mux/DeMux switch connected to the twin TAP and the I2C bus and responsive to the SOC or the MCU for selective switching of the test data along either the TAP-X or TAP-Y direction to a predetermined port associated with one of the multiple devices.

Claims16

Dependent claims

A switch-mode interposer arrangement for boundary-scan testing of a Multi-Chip Module (MCM) having a System-On-Chip (SOC), a Microprocessor Control Unit (MCU), and multiple chiplets based devices including Central Processing Units (CPUs), graphical processing units (GPUs), and/or memory devices disposed on a stacked or two-tiered interposer-substrate system, comprising:

(a) A twin Test Access Port (TAP) operatively connected to a JTAG controller and configured to transmit test data in one direction defined as TAP-X and an opposite direction defined as TAP-Y along an Inter-Integrated Circuit (I2C) bus connected with the SOC, the MCU and the multiple devices, the test data being formatted pursuant to IEEE 1149.1 (i.e., JTAG) or IEEE 1149.7 standard (i.e., cJTAG);
and
(b) a Mux/DeMux switch mechanism connected to the twin TAP and the I2C bus and responsive to the SOC or the MCU for selective switching of the test data along either the TAP-X or TAP-Y direction to a predetermined port associated with one of the multiple devices in the MCM.

A method for boundary-scan testing of a Multi-Chip Module (MCM) having a System-On-Chip (SOC), a Microprocessor Control Unit (MCU), and multiple chiplets based devices including central processing units (CPUs), graphical processing units (GPUs), and/or memory devices disposed on a stacked or two-tiered interposer-substrate system, comprising:

(a) configuring a JTAG controller-based Test Access Ports (TAPs) to transmit test data in one direction defined as TAP-X for a TAP-X based daisy chain and an opposite direction defined as TAP-Y for a TAP-Y based daisy chain along with an Inter-Integrated Circuit (I2C) bus connecting the SOC, and the MCU and the multiple devices, the test data being formatted according to IEEE 1149.1 (i.e., JTAG) or IEEE 1149.7 standard (i.e., cJTAG);
and
(b) switching by using a Mux/DeMux switch mechanism connected to the twin TAP and the I2C bus and by responding to the SOC or MCU for selective switching of the test data along either the TAP-X or TAP-Y based daisy-chains, to a predetermined port associated with one of the multiple devices in the MCM.

Dependencies are inferred from the claim text.

Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Without Known Good Die

Life of this patent

Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Without Known Good Die

Life of this patent

Abstract

Claims16