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US 2021/0333325 A1Published application
Interface to full and reduced pin jtag devices
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
Claims12
Interface circuitry comprising:
- (a) a first port having a first data in pin, a first data out pin, a first clock in pin, and a first mode select in pin;
- (b) a second port having a second data out pin coupled to the first data in pin, a second data in pin coupled to the first data out pin, a second clock out pin coupled to the first clock out pin, and a second mode select out pin coupled to the first mode select in pin;
- and
- (c) a third port having a third clock out pin coupled with the first clock in pin, and a third data in and out pin coupled with the first mode select in pin.
1 more element
An integrated circuit comprising:
- (a) full pin circuitry including a full pin interface, the full pin interface having a data in pin, a data out pin, a clock in pin, and mode select in pin;
- (b) reduced pin circuitry including a reduced pin interface, the reduced pin interface having a data in and out pin and a clock in pin;
- and
- (c) a full pin and reduced pin interface circuit including:
- a first port of pins having a data in pin, a data out pin, a clock in pin, and a mode select in pin;
- a second port of pins coupled to the full pin interface;
- and
- a third port of pins coupled to the reduced pin interface.
5 more elements
Dependencies are inferred from the claim text.