Improved jtag registers with concurrent inputs

An apparatus, comprising:

• a host device or a system-on-chip (SoC);
• a memory component having an independent structure and including an array of memory cells, organized in sub arrays, with associated decoding and sensing circuitry;
• a joint test action group (JTAG) interface in the array of memory cells including a boundary scan architecture;
• and
• an instruction register in the boundary scan architecture of the JTAG interface including a couple of bits indicative of a presence of a test data input (TDI) signal.

A device, comprising:

• a memory component, having an independent structure couplable to a host device or a system-on-ship (SoC), including an array of memory cells organized in sub arrays with associated decoding and sensing circuitry;
• a joint test action group (JTAG) interface in the array of memory cells including a boundary scan architecture;
• and
• an instruction register in the boundary scan architecture of the JTAG interface includes a couple of bits indicative of a presence of a test data input (TDI) signal.

A method, comprising:

• providing a joint test action group (JTAG) finite state machine (FSM) interface or a reduced instruction set computer (RISC) controller in a memory array;
• selecting an instruction register in a boundary scan architecture of the JTAG FSM interface or RISC controller;
• and
• loading at least a couple of bits of the instruction register indicative of a presence of a test data input (TDI) signal in a single clock cycle and in parallel with data of memory cells of the memory array.