Diffusion barrier layer in programmable metallization cell

An integrated chip comprising:

• a substrate;
• a bottom electrode via overlying the substrate;
• and
• a programmable metallization cell overlying the bottom electrode via, wherein the programmable metallization cell comprises a top electrode, a data storage layer, an active metal layer, and a diffusion barrier layer, wherein the top electrode comprises a diffusive species, wherein the top electrode has a lower reactivity to oxygen than the active metal layer, wherein the active metal layer is disposed between the top electrode and the data storage layer, and wherein the diffusion barrier layer underlies the top electrode and is configured to prevent diffusion of the diffusive species to the data storage layer.

A method for forming a memory device, the method comprising:

• forming a lower conductive wire over a substrate;
• forming a bottom electrode via over the lower conductive wire;
• forming a memory cell layer stack over the bottom electrode via, wherein the memory cell layer stack includes a bottom electrode, a data storage layer, a diffusion barrier layer, and a top electrode, wherein the diffusion barrier layer is disposed between the data storage layer and the top electrode, wherein the top electrode comprises a diffusive species, and wherein the diffusion barrier layer is configured to block diffusion of the diffusive species;
• and
• patterning the memory cell layer stack, thereby defining a programmable metallization cell.