Phase-change memory cell having a compact structure

A memory, comprising:

• a plurality of wordlines;
• a plurality of bit lines;
• a plurality of source lines;
• a semiconductor substrate;
• a first insulating layer covering a surface of the semiconductor substrate;
• a semiconductor active layer covering the first insulating layer;
• a first memory cell including:
• a control gate of a first selection transistor, the control gate being on the active layer and having a lateral flank;
• a second insulating layer covering the lateral flank of the control gate;
• first and second conduction regions of the first selection transistor, the first and second conduction regions being in the active layer;
• and
• a variable-resistance element electrically coupled to first conduction region of the first selection transistor and including:
• a first layer of resistive material extending in the active layer and contacting the first conduction region, and
• a second layer contacting the first layer, wherein second layer is a variable-resistance material.

A memory, comprising:

• a semiconductor substrate;
• a first insulating layer on the semiconductor substrate;
• an active layer of a semiconductor material on the first insulating layer;
• a control gate of a first selection transistor on the active layer and having a lateral flank;
• a second insulating layer covering the lateral flank of the control gate;
• first and second conduction regions of the first selection transistor in the active layer;
• a trench in the active layer and defined on a first side by a first lateral flank of the active layer and reaching the first insulating layer;
• a heater layer of resistive material in the trench covering the first lateral flank of the active layer;
• and
• a layer of a variable resistance material in contact with the heater layer, electrically coupled to the first conduction terminal, the heater layer of resistive material is configured to heat the layer of the variable resistance material.