Bandgap reference circuit including vertically stacked active soi devices

An integrated circuit, comprising:

• a bandgap reference circuit for generating a reference current, the bandgap reference circuit comprising:
• first and second vertically stacked structures, the first and second vertically stacked structures each including:
• a P-type substrate;
• a P-well region within the P-type substrate;
• an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction;
• a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET, wherein the FET in the first vertically stacked structure and the FET in the second vertically stacked structure form a current mirror;
• and
• a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region, wherein the first voltage source concurrently biases the back gate of the FET.

A bandgap reference circuit with vertically stacked active silicon-on-insulator (SOI) devices, comprising:

• a P-type substrate;
• a P-well region within the P-type substrate;
• an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction;
• a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET;
• and
• a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region, wherein the first voltage source concurrently biases the back gate of the FET.