Semiconductor Structure Cutting Process and Structures Formed Thereby

A semiconductor structure comprising:

• a first semiconductor fin and a second semiconductor fin on a substrate, the first semiconductor fin and the second semiconductor fin being longitudinally aligned;
• isolation regions along opposing sides of the first semiconductor fin and the second semiconductor fin;
• a first source/drain region in the first semiconductor fin;
• a second source/drain region in the second semiconductor fin;
• an isolation structure between the first semiconductor fin and the second semiconductor fin, the isolation structure comprising:
• a first dielectric liner extending along a first sidewall of the first semiconductor fin and a second sidewall of the second semiconductor fin;
• and
• a dielectric fill on a first sidewall of the first dielectric liner and on a second sidewall of the first semiconductor fin, the first dielectric liner further being on a surface of the first semiconductor fin between the first sidewall of the first semiconductor fin and the second sidewall of the first semiconductor fin.

A semiconductor structure comprising:

• a first semiconductor fin and a second semiconductor fin on a substrate, the first semiconductor fin and the second semiconductor fin being longitudinally aligned along a first longitudinal axis;
• a first gate structure and a second gate structure, the first gate structure and the second gate structure being longitudinally aligned along a second longitudinal axis, wherein the first longitudinal axis intersects the second longitudinal axis;
• isolation regions along opposing sides of the first semiconductor fin and the second semiconductor fin;
• a first source/drain region in the first semiconductor fin;
• a second source/drain region in the second semiconductor fin;
• an isolation structure between the first semiconductor fin and the second semiconductor fin, the isolation structure being interposed between the first gate structure and the second gate structure, the isolation structure comprising:
• a first dielectric liner extending along a first sidewall of the first semiconductor fin and a second sidewall of the second semiconductor fin;
• and
• a dielectric fill on a first sidewall of the first dielectric liner and on a second sidewall of the first semiconductor fin, wherein the first dielectric liner is interposed between the first gate structure and the dielectric fill, wherein the first dielectric liner is interposed between the second gate structure and the dielectric fill.