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US 2021/0280694 A1Published application
Liner for A Bi-Layer Gate Helmet and the Fabrication Thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHuan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
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Abstract
A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
Claims20
A method, comprising:
- providing a semiconductor device that includes:
- a semiconductor fin structure;
- source/drain regions disposed on opposite sides of the semiconductor fin structure;
- a gate structure disposed over the semiconductor fin structure;
- gate spacers disposed on sidewalls of the gate structure;
- and
- etching the semiconductor device, wherein the gate structure is etched at a faster rate than the gate spacers during the etching;
- and
- after the etching, forming a liner over the gate structure and the gate spacers.
6 more elements
A method, comprising:
- providing a semiconductor device that includes:
- a semiconductor fin structure;
- source/drain regions disposed on opposite sides of the semiconductor fin structure;
- a gate structure disposed over the semiconductor fin structure;
- gate spacers disposed on sidewalls of the gate structure;
- and
- an interlayer dielectric (ILD) structure disposed on sidewalls of the gate spacers;
- performing a first etching process to the semiconductor device, wherein an etching selectivity exists between the gate structure, the gate spacers, and the ILD structure during the first etching process, such that remaining portions of the gate structure, the gate spacers, and the ILD structure collectively define a T-shaped opening;
- and
- after the first etching process has been performed, partially filling the T-shaped opening with a liner, over the gate structure and the gate spacers.
7 more elements
A method, comprising:
- providing a semiconductor device that includes:
- a source and a drain;
- a semiconductor structure disposed between the source and the drain;
- a first metal layer disposed over the semiconductor structure;
- an interlayer dielectric (ILD) disposed over the source and over the drain;
- and
- spacers disposed between the ILD and the first metal layer;
- performing one or more first etching processes to form an opening in the semiconductor device, wherein the opening is defined by an upper surface of the first metal layer, upper surfaces and side surfaces of the spacers, and side surfaces of the ILD;
- forming a liner to partially fill the opening, wherein the liner has a first material composition (e.g., a high-k material);
- forming a dielectric material on the liner, the dielectric material having a second material composition (e.g., SiN) different from the first material composition;
- and
- performing a second etching process to remove the dielectric material, wherein the dielectric material has a greater etching rate than the liner such that the liner protects at least the spacers from being etched during the second etching process.
9 more elements
Dependencies are inferred from the claim text.