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US 2021/0280692 A1Published application
Reducing Metal Gate Overhang By Forming A Top-Wide Bottom-Narrow Dummy Gate Electrode
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
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Abstract
A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
Claims20
A method, comprising:
- forming a dummy gate electrode layer over a gate dielectric layer;
- forming a patterned mask layer over the dummy gate electrode layer;
- patterning, using the patterned mask layer as a mask, the dummy gate electrode layer into a plurality of patterned dummy gate electrodes that are spaced apart from one another, such that each of the patterned dummy gate electrodes has a top-wide-bottom-narrow profile in a cross-sectional side view, wherein the patterning includes etching the dummy gate electrode layer with increasingly stronger lateral etching characteristics;
- forming gate spacers on sidewalls of the patterned dummy gate electrodes;
- and
- replacing the patterned dummy gate electrodes with metal-containing gate electrodes.
3 more elements
A method, comprising:
- forming a gate dielectric layer over a substrate;
- forming a dummy gate electrode layer over the gate dielectric layer;
- patterning, via a plurality of etching processes, the dummy gate electrode layer into a plurality of patterned dummy gate electrodes, wherein the plurality of etching processes is performed with increasingly stronger lateral etching characteristics, such that the patterned dummy gate electrodes each have a tapered cross-sectional profile where an upper portion of the patterned dummy gate electrode is wider than a lower portion of the patterned dummy gate electrode;
- forming gate spacers on sidewalls of the patterned dummy gate electrodes;
- removing the patterned dummy gate electrodes, thereby forming a plurality of openings defined at least in part via the gate spacers;
- and
- filling the plurality of openings with a metal-containing gate electrode layer.
4 more elements
A method, comprising:
- forming an un-patterned dummy gate structure over a substrate;
- performing a first etching process on the un-patterned dummy gate structure, wherein the first etching process has a first lateral etching characteristic;
- after the first etching process, performing a second etching process on the un-patterned dummy gate structure, wherein the second etching process has a second lateral etching characteristic that is greater than the first lateral etching characteristic;
- after the second etching process, performing a third etching process on the un-patterned dummy gate structure, wherein the third etching process has a third lateral etching characteristic that is greater than the second lateral etching characteristic, and wherein the un-patterned dummy gate structure is etched into a plurality of patterned dummy gate structures that are separated from one another after the third etching process has been performed;
- forming gate spacers on sidewalls of the patterned dummy gate structures;
- and
- replacing the patterned dummy gate structures with metal-containing gate structures.
4 more elements
Dependencies are inferred from the claim text.