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US 2021/0280688 A1Published application
Nanosheet transistor
AssigneeTessera, Inc.
InventorsKangguo Cheng, Juntao LI, Heng Wu, Peng Xu
Life of this patent
Estimating the term…
Abstract
Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.
Claims20
A semiconductor integrated circuit comprising:
- a nanosheet stack comprising:
- a first semiconductor layer;
- a second semiconductor layer, the second semiconductor layer disposed above and separated from the first semiconductor layer;
- a first pair of inner spacers underpinning opposite sides of the first semiconductor layer;
- and
- a second pair of inner spacers between the first semiconductor layer and the second semiconductor layer, the second pair of inner spacers underpinning opposite sides of the second semiconductor layer;
- a first source-drain region on a first side of the nanosheet stack, the first source-drain region contacting (i) the first semiconductor layer, (ii) the second semiconductor layer, and (iii) an inter-source-drain dielectric region on a first side of the inter-source-drain dielectric region;
- a second source-drain region on a second side of the inter-source-drain dielectric region opposite the first side of the inter-source-drain dielectric region, the second source-drain region contacting the inter-source-drain dielectric region;
- and
- a high-k gate dielectric layer and a work-function metal layer on the first and second semiconductor layers and between the first and second semiconductor layers.
7 more elements
A semiconductor integrated circuit comprising:
- a first nanosheet fin extending in a first direction and comprising at least a first semiconductor nanosheet and a second semiconductor nanosheet, the first nanosheet fin further comprising:
- a first pair of inner spacers disposed under and contacting the first semiconductor nanosheet;
- and
- a second pair of inner spacers (i) disposed above and contacting the first semiconductor nanosheet and (ii) disposed under and contacting the second semiconductor nanosheet;
- a second nanosheet fin adjacent to the first nanosheet fin and extending in the first direction, the second nanosheet fin comprising at least a third semiconductor nanosheet and a fourth semiconductor nanosheet, the second nanosheet fin further comprising:
- a third pair of inner spacers disposed under and contacting the third semiconductor nanosheet;
- and
- a fourth pair of inner spacers (i) disposed above and contacting the third semiconductor nanosheet and (ii) disposed under and contacting the fourth semiconductor nanosheet;
- a gate structure extending in a second direction substantially perpendicular to the first direction, the gate structure disposed over and between the first and second nanosheet fins, including over and between the first, second, third, and fourth semiconductor nanosheets, the gate structure comprising outer spacers in regions above the first and second nanosheet fins;
- an inter-source-drain dielectric region extending in the second direction;
- a first source-drain region extending in the second direction on a first side of the inter-source-drain dielectric region and contacting the inter-source-drain dielectric region, the first source-drain region contacting (i) the first, second, third, and fourth semiconductor nanosheets and (ii) the first, second, third, and fourth pairs of inner spacers;
- and
- a second source-drain region extending in the second direction on a second side of the inter-source-drain dielectric region opposite the first side of the inter-source-drain dielectric region, the second source-drain region contacting the inter-source-drain dielectric region.
10 more elements
Dependencies are inferred from the claim text.