Field effect transistor structures
AssigneeTessera, Inc.
InventorsJosephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
Life of this patent
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Abstract
Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.
Claims22
A method of forming a semiconductor device, comprising:
- providing sacrificial layers and channel layers over a substrate, wherein the sacrificial layers alternate with channel layers;
- etching through the sacrificial layers and the channel layers to form a fin;
- forming a plurality of dummy gates over the fin, wherein the plurality of dummy gates comprises at least three dummy gates where two adjacent dummy gates comprise (i) an outside dummy gate over an end of the fin and (ii) a central dummy gate over an interior portion of the fin;
- etching through the sacrificial layers and the channel layers using the dummy gates as a mask, wherein the etching leaves a plurality of exposed surfaces of the channel layers and a plurality of exposed surfaces of the sacrificial layers bordering a gap between the outside dummy gate and the central dummy gate;
- and
- epitaxially growing source/drain material on the plurality of exposed surfaces of the channel layers,
- wherein source/drain material grown on channel layers merges with source/drain material grown on vertically adjacent channel layers, and
- wherein source/drain material grown on channel layers does not merge with source/drain material grown on laterally adjacent channel layers.
A method of forming a semiconductor device, the method comprising:
- providing sacrificial layers and channel layers over a substrate, wherein the sacrificial layers alternate with channel layers, wherein a lowermost layer is a sacrificial layer, and wherein an uppermost layer is a sacrificial layer;
- etching through the sacrificial layers and the channel layers to form a fin;
- forming a plurality of dummy gates over the fin, wherein the plurality of dummy gates comprises at least three dummy gates where two adjacent dummy gates comprise (i) an outside dummy gate over an end of the fin and (ii) a central dummy gate over an interior portion of the fin;
- etching through the sacrificial layers and the channel layers using the dummy gates as a mask, wherein the etching leaves a plurality of exposed surfaces of the channel layers and a plurality of exposed surfaces of the sacrificial layers bordering a gap between the adjacent outside dummy gate and the central dummy gate;
- epitaxially growing source/drain material on the plurality of exposed surfaces of the channel layers, wherein source/drain material grown on channel layers merges with source/drain material grown on vertically adjacent channel layers;
- and
- filling a remaining gap between merged source/drain material on the channel layers of the central dummy gate and merged source/drain material on the channel layers of the outside dummy gate with a dielectric.
Dependencies are inferred from the claim text.