Integrated Assemblies Having Vertically-Spaced Channel Material Segments, and Methods of Forming Integrated Assemblies
AssigneeMicron Technology, Inc.
InventorsJohn D. Hopkins, Shyam Surthi
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsJohn D. Hopkins, Shyam Surthi
Estimating the term…
Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have primary regions of a first vertical thickness, and have terminal projections of a second vertical thickness which is greater than the first vertical thickness. The terminal projections include control gate regions. Charge-blocking regions are adjacent the control gate regions, and are vertically spaced from one another. Charge-storage regions are adjacent the charge-blocking regions and are vertically spaced from one another. Gate-dielectric material is adjacent the charge-storage regions. Channel material is adjacent the gate dielectric material. Some embodiments included methods of forming integrated assemblies.
1-22. (canceled)
A method of forming an integrated structure, comprising:
Dependencies are inferred from the claim text.