Integrated Assemblies and Methods of Forming Integrated Assemblies

An integrated assembly, comprising:

• a memory array region which includes channel material pillars extending through a stack of alternating conductive levels and insulative levels;
• a staircase region offset from the memory array region and comprising regions of the conductive levels;
• an interconnect region between the memory array region and the staircase region;
• a first conductive expanse within the memory array region and electrically coupled with the channel material of the channel material pillars;
• a second conductive expanse within the staircase region at a same elevational level as the first conductive expanse;
• and
• a panel extending across the memory array region, the interconnect region and the staircase region;
• the panel separating one memory block region from another;
• the panel having a first portion supported by a region of the first conductive expanse, a third portion supported by a region of the second conductive expanse, and a second portion between the first and third portions;
• the second portion having a bottom surface which is elevationally offset relative to bottom surfaces of the first and third portions.

A method of forming an integrated assembly, comprising:

• forming a construction having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region;
• the construction comprising a first conductive expanse in the memory array region and a second conductive expanse in the staircase region;
• the first and second conductive expanses being at a first elevational level;
• the construction comprising conductive blocks in the intervening region, the conductive blocks being at the first elevational level;
• the construction comprising a gap between the first and second expanses in the intervening region, and comprising a bridging structure extending across said gap;
• the bridging structure being at a second elevational level which is different from the first elevational level;
• forming a stack of alternating first and second levels over the construction;
• the first levels comprising sacrificial material and the second levels comprising insulative material;
• forming channel material pillars to extend through the stack in the memory array region;
• the channel material of the channel material pillars being electrically coupled with the first conductive expanse;
• forming a slit to extend through the stack;
• the slit having a first portion along the first conductive expanse of the memory array region, having a second portion along the bridging structure of the intervening region, and having a third portion along the second expanse of the staircase region;
• the slit spacing a first memory block region from a second memory block region;
• removing the sacrificial material and replacing it with conductive material;
• and
• forming one or more materials within the slit.