Non-volatile memory (nvm) cell structure to increase reliability

An integrated chip comprising:

• a well region disposed within a substrate;
• an isolation structure disposed within a front-side surface of the substrate, wherein the isolation structure laterally surrounds the well region;
• a bit line write region disposed within the well region;
• a bit line read region disposed within the well region and laterally offset from the bit line write region by a non-zero distance;
• a first storage transistor comprising source/drain regions disposed within the bit line write region and a first gate electrode comprised of a first floating gate portion of a floating gate, wherein the source/drain regions of the first storage transistor are disposed on opposing sides of the floating gate, wherein the floating gate overlies the well region of the substrate;
• and
• a second storage transistor comprising source/drain regions disposed within the bit line read region and a second gate electrode comprised of a second floating gate portion of the floating gate, wherein the source/drain regions of the second storage transistor are disposed on the opposing sides of the floating gate.

A method for forming a memory device, the method comprising:

• forming an isolation structure in a substrate, wherein the isolation structure comprises inner sidewalls that demarcate a device region of the substrate;
• doping the substrate to form a middle well region within the device region of the substrate;
• forming a floating gate over at least a portion of the middle well region and at least a portion of the isolation structure;
• and
• doping the substrate to form a bit line read region within a first portion of the middle well region and a bit line write region within a second portion of the middle well region, wherein the bit line read region includes source/drain regions on opposite sides of the floating gate and the bit line write region includes source/drain regions on the opposite sides of the floating gate, wherein the first portion of the middle well region is laterally offset from the second portion of the middle well region by a non-zero distance.