Non-volatile memory (nvm) cell structure to increase reliability

A memory cell comprising:

• a first capacitor including a first capacitor plate comprised of a first capacitor active region disposed within a substrate and a second capacitor plate comprised of a first floating gate portion of a floating gate, wherein the floating gate overlies the substrate, and wherein the first capacitor active region is a doped region of the substrate and comprises a first doping type;
• a second capacitor including a first capacitor plate comprised of a second capacitor active region disposed within the substrate and a second capacitor plate comprised of a second floating gate portion of the floating gate;
• a plurality of transistors overlying the substrate, wherein the transistors include:
• a first storage transistor including source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate, wherein the bit line write region is disposed within the substrate;
• and
• a second storage transistor including source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate, wherein the bit line read region is disposed within the substrate and is laterally offset from the bit line write region by a non-zero distance.