Anti-fuse device method and layout

A method of manufacturing an anti-fuse device, the method comprising:

• forming a plurality of source/drain (S/D) structures in an active area of a substrate;
• forming first and second transistors, the first and second transistors sharing a first S/D structure of the plurality of S/D structures;
• forming a first anti-fuse structure, the first anti-fuse structure and the first transistor sharing a second S/D structure of the plurality of S/D structures;
• forming a second anti-fuse structure, the second anti-fuse structure and the second transistor sharing a third S/D structure of the plurality of S/D structures;
• forming a third transistor, the third transistor and the first anti-fuse structure sharing a fourth S/D structure of the plurality of S/D structures;
• and
• forming a fourth transistor, the fourth transistor and the second anti-fuse structure sharing a fifth S/D structure of the plurality of S/D structures.

A method of generating an integrated circuit (IC) layout diagram, the method comprising:

• intersecting an active region with first, second, and third gate regions, thereby defining a location of a first anti-fuse structure between first and second transistors;
• overlying the active region with first and second contact regions, the first, second, and third gate regions being between the first and second contact regions;
• overlying the active region and first and second contact regions with a first conductive region;
• and
• storing the IC layout diagram comprising the active region, the first, second, and third gate regions, the first and second contact regions, and the first conductive region in a storage device.