Semiconductor memory device

A semiconductor memory device comprising:

• a memory region on a semiconductor substrate, in which a memory cell array is formed;
• and
• a peripheral circuit region on the semiconductor substrate, in which a peripheral circuit is formed, wherein
• the peripheral circuit region is formed with at least one MOS transistor,
• the MOS transistor includes a first diffusion layer and a second diffusion layer that are disposed with a predetermined interval in a first direction parallel to a surface of the semiconductor substrate, the MOS transistor further including at least one gate wiring disposed between the first diffusion layer and the second diffusion layer, the at least one gate extending in a second direction orthogonal to the first direction,
• a first contact region is formed on a surface of the first diffusion layer, the first contact region being connected with a first plug configured to electrically connect the first diffusion layer and a first wiring formed in a wiring layer located vertically above the semiconductor substrate,
• a second contact region is formed on a surface of the second diffusion layer, the second contact region being connected with a second plug configured to electrically connect the second diffusion layer and a second wiring formed in the wiring layer, and
• when viewed in the first direction, the first contact region has a region that does not overlap with the second contact region, and the second contact region has a region that does not overlap with the first contact region.