Three-dimensional (3d), vertically-integrated field-effect transistors (fets) electrically coupled by integrated vertical fet-to-fet interconnects for complementary metal-oxide semiconductor (cmos) cell circuits

A method of fabricating a complementary metal-oxide semiconductor (CMOS) cell circuit, the method comprising:

• forming a first semiconductor layer comprising a first Field-Effect Transistor (FET), comprising:
• forming a first semiconductor channel structure extending longitudinally in a length direction and extending in a width direction orthogonal to the length direction;
• forming a second semiconductor layer comprising a second FET above the first FET in a vertical direction orthogonal to the length direction and the width direction, comprising:
• forming a second semiconductor channel structure above the first semiconductor channel structure in the vertical direction, the second semiconductor channel structure extending longitudinally in the length direction and extending in the width direction;
• and
• forming a vertical FET-to-FET interconnect extending in the vertical direction directly between a first terminal region of the first FET and a first terminal region of the second FET and without extending beyond the first terminal region of the second FET in the vertical direction, the vertical FET-to-FET interconnect electrically coupling the first terminal region of the first FET and the first terminal region of the second FET.